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Altera_Forum
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15 years ago

Cylone II FPGA Clock input

In my design ，the FPGA uses single-end clock input, the clock is 40MHz signal ,3.3 Vpp and 6.6Vpp , the Voltage is -1.55~+1.55V and -3.3~+3.3V, but the FPGA I/O Voltage :-0.8V~4.1V. My ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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I can't understand you. What is "3.3 Vpp and 6.6Vpp , the Voltage is -1.55~+1.55V and -3.3~+3.3V, but the FPGA". If you clock generator is 3.3v you can connect this clock to 3.3v powered bank fpga.

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The two clock signals are 40MHz,3.3Vpp and 40MHz,6.6Vpp ,but the Voltage is not from 0V~3.3V and 0V~6.6V, 3.3Vpp means -1.55~+1.55V and 6.6Vpp means

-3.3~+3.3V, I don't know the clock source is usefull for the EP2C70F896C8??