Honored Contributor
Honored ContributorAs the ARM is a 32-bit processor, as well as all the peripheral bridges, that's a really good question. The fast bridge is itself tied to a 64-bit bus to the main L3 switch. I could imagine the bridge AXI management unit can pack data together if configured for it, but I'd think that would require custom instructions?
Check out page 8-18 in the HPS TRM: "The master issuing capability can be adjusted, through the fn_mod register, to allow one or multiple transactions to be outstanding in the FPGA fabric. The master bypass merge feature can also be enabled, through the bypass_merge bit in the fn_mod2 register. This feature ensures that the upsizing and downsizing logic does not alter any transactions when the FPGA master interface is configured to be 32 or 128 bits wide." This seems to say that it is worth looking at those two registers to see what their settings are. I'd think you'd WANT the merging to happen, which might not be on by default? That's a U-boot/preloader question, right there. I'd love to hear more, though. instead of a memcpy_toio(), have you tried a 64-bit transaction in a loop or direct?
