CycloneV DDR3 Hard Controller: Many Failing Timing Paths

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Hard controller implemented in Platform Designer (PD)

Rest of design passes timing

I've read through the EMI.pdf (External Memory Interface Handbook)

It looks like the PD generated sdc files are in the .qip, and this is included in the project settings files

All of the failing paths are internal to the logic included with the hard controller.

Memory clock: 400MHz (max), Device speed grade is 7 (this is fastest industrial temp)
Is this combination not possible? Is this listed somewhere?

Any suggestions on how to resolve this is appreciated.