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New Contributor

4 years ago

CycloneV DDR3 Hard Controller: Many Failing Timing Paths

5CSEMA5F31I7N Hard controller implemented in Platform Designer (PD) Rest of design passes timing I've read through the EMI.pdf (External Memory Interface Handbook) It looks like the PD genera...

yoichiK_altera

Contributor

4 years ago

Per EMIF spec estimator speed grad of 7 support 400Mhz of DDR3. Which path is failing ? Are launch and latch clock are same clock resource ?

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support/emif.html

JPB3RD
New Contributor
4 years ago
Thank you for your reply. The issue has been resolved and I posted this.

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CycloneV DDR3 Hard Controller: Many Failing Timing Paths

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