Forum Discussion
JPB3RD
New Contributor
New ContributorCycloneV DDR3 Hard Controller: Many Failing Timing Paths
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Hard controller implemented in Platform Designer (PD)
Rest of design passes timing
I've read through the EMI.pdf (External Memory Interface Handbook)
It looks like the PD genera...
yoichiK_altera
Contributor
ContributorHi
Per EMIF spec estimator speed grad of 7 support 400Mhz of DDR3. Which path is failing ? Are launch and latch clock are same clock resource ?
- JPB3RD
Thank you for your reply. The issue has been resolved and I posted this.
