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JPB3RD
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4 years ago

CycloneV DDR3 Hard Controller: Many Failing Timing Paths

5CSEMA5F31I7N Hard controller implemented in Platform Designer (PD) Rest of design passes timing I've read through the EMI.pdf (External Memory Interface Handbook) It looks like the PD genera...
JPB3RD's avatar
JPB3RD
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4 years ago

This issue is resolved. Just to close this out in case it helps someone else, changing the input clock to the DDR3 controller from 200MHz to 100MHz caused all the timing paths to pass (!?). Strangest thing and I'm moving on :-).