Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Cycloneiii Flip Flop mistery

Hello!

I have a cycloneiii starterkit board from altera and terasic. This little one has a RS232 interface in the PIN_E18 and PIN_H17 , RXD and TXD respectively. I test the pins by making a loopback:

architecture loopback of uart is

beginTx <= Rx;

end loopback;

Which works just fine ( I can see in my favorite xxxxxxterminal software an echoed character).

Next test... let's interface them with a flip:

architecture loopback_registered of uart is

beginlb_reg: process (clk,rst)

beginif rst='1' then Tx <= '1' then --- Line always at one!

elseif rising_edge(clk)Tx <= Rx; -- Lets sample incoming Rxd!

end if;

[/INDENT]end process;

[/INDENT]end loopback_registered;

BUT IT DOES NOT WORK! :eek:, In the simulation works fine (in order to discard clk and reset miss assignments).

So I focused in the following two questions::rolleyes:

1. ¿ Does anyone knows what Am I doing wrong at a RTL level :D?.

2. If nothing wrong with it... Is there any feature quartus have in order to make a clk is not arriving properly to the flip's clk gate :confused: ?

Im using a EP3C25F324C6. Cycloneiii FPGA starter board kit.

I also tried to register a button into a led.... etc... but neither did it work.

Regards to everyone!!!

And Thank You!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    First what is your clk speed?

    second, do you do physical loop back or just inside fpga. How do you read back Tx pin (is it bidirectional)?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    As an obvious explanation, either rst or clk isn't driven correctly.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    Hello!

    architecture loopback_registered of uart is

    beginlb_reg: process (clk,rst)beginif rst='1' thenTx <= '1'; -- then --- Line always at one!elseif rising_edge(clk) thenTx <= Rx; -- Lets sample incoming Rxd!end if;

    end if;

    [/INDENT]end process;

    [/INDENT]end loopback_registered;

    --- Quote End ---

    I changed some syntax errors in the quote above (highlighted in red).

    Possible causes why this does not work:

    1) did you update the pin assignments for your clk and rst signals? Make sure that you do not have unconnected pins?

    2) did you check that you did not use an "inverted" rst signal (e.g. from an active high KEY on your board)?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    First what is your clk speed?

    second, do you do physical loop back or just inside fpga. How do you read back Tx pin (is it bidirectional)?

    --- Quote End ---

    Im using a 50 MHz clock.

    Those pins are PIN_E18 and PIN_H17, Rx Input and Tx output respectively, in the EP3C25F324C6. Those are not biderectional.