--- Quote Start ---
Hello!
architecture loopback_registered of uart is
beginlb_reg: process (clk,rst)beginif rst='1' thenTx <= '1'; -- then --- Line always at one!elseif rising_edge(clk) thenTx <= Rx; -- Lets sample incoming Rxd!end if;
end if;
[/INDENT]end process;
[/INDENT]end loopback_registered;
--- Quote End ---
I changed some syntax errors in the quote above (highlighted in red).
Possible causes why this does not work:
1) did you update the pin assignments for your
clk and
rst signals? Make sure that you do not have unconnected pins?
2) did you check that you did not use an "inverted" rst signal (e.g. from an active high KEY on your board)?
Honored Contributor
