Cyclone10LP SEU CRC error implementation

Hi Gorka,

For the CRC data output which is actually regout signal is the output of the error detection (i.e., the cyclone10lp_crcblock) shift register synchronized to the clk port to be read by the core logic. It shifts one bit at each cycle, so you should clock the clk signal 31 cycles to read out the 32 bits of the shift register.

Note: Any soft error failure affects the user logic. Therefore, do not rely on the regout signal in the 32-bit CRC signature to detect a soft error. The CRC_ERROR output signal provides a more accurate reading because is it not affected by a soft error.

Also, I do not see any attachments in the previous comments also.

For the SEU License, how you have registered/applied for it? Please contact in your regional FAE or sales representative. If not able to, please let me know the complete details then only I will be able to help it.

Thank you,

Kshitij Goel