New ContributorHi, Intel:
I am new to C10gx, and I'm learning to use ATX PLL ip core, aim to learn to achieve using SFP+ interface at 10Gbps data rate.
I meet the warning message like this when I am trying to output "tx_serial_clk0" signal,do you konw why? And how can i make sure the ATX PLL ip core is working like i want it to?
Thanks,
Li.
Regular ContributorHi,
The main reason for failure is that the transceivers have their own clock networks which are completely separated from the regular FPGA fabric, so transceiver clock ports cannot be top-level ports.
To get rid of this error you need to connect the pll output clock to a transceiver block.
Regards
New ContributorHi,
Thanks for your reply.
I try to connect the pll output clock--tx_serial_clk0 to the Transceiver Native PHY IP core in the following project:
When I am learning to use SFP+ interface of Cyclone 10 GX board,I designed the project with ATX PLL IP core、Reset Controller IP Core 、Cyclone 10 GX Transceiver Native PHY, and connected them like the user guide said:
Then I use Modelsim to simulate the whole project,but I can't check the "tx_serial_data"as expected,it's always 0. Then I find the "tx_clkout" and the "rx_clkout" are always 0 ,too.But I can't check the "tx_serial_clk0" signal.
Could you help me to check the problem? Did I use the IP Core in a wrong way?Did the ATX PLL IP core worked as expected?
Thanks.
Regular ContributorHi,
Please attach the Quartus project to replicate the issue.
Regards
New ContributorHi,
There is my project, in Quartus Pro 17.1.0.240.I can't compile it successfully.
Thanks,
Li
Regular ContributorI do not receive any response from you to the previous private message. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
