Forum Discussion
New ContributorCyclone10 GX:About ATX PLL ip core.
Regular ContributorHi,
The main reason for failure is that the transceivers have their own clock networks which are completely separated from the regular FPGA fabric, so transceiver clock ports cannot be top-level ports.
To get rid of this error you need to connect the pll output clock to a transceiver block.
Regards
New ContributorHi,
Thanks for your reply.
I try to connect the pll output clock--tx_serial_clk0 to the Transceiver Native PHY IP core in the following project:
When I am learning to use SFP+ interface of Cyclone 10 GX board,I designed the project with ATX PLL IP core、Reset Controller IP Core 、Cyclone 10 GX Transceiver Native PHY, and connected them like the user guide said:
Then I use Modelsim to simulate the whole project,but I can't check the "tx_serial_data"as expected,it's always 0. Then I find the "tx_clkout" and the "rx_clkout" are always 0 ,too.But I can't check the "tx_serial_clk0" signal.
Could you help me to check the problem? Did I use the IP Core in a wrong way?Did the ATX PLL IP core worked as expected?
Thanks.
