Cyclone V SoC HPS2FPGA AXI Master - How to enable?

the same method as lw-axi, change the offset only as follows.

# define ALT_AXI_FPGASLVS_OFST (0xC0000000) // axi_master

# define HW_FPGA_AXI_SPAN (0x40000000) // Bridge span

# define HW_FPGA_AXI_MASK ( HW_FPGA_AXI_SPAN - 1 )

axi_virtual_base = mmap( NULL, HW_FPGA_AXI_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd,ALT_AXI_FPGASLVS_OFST );

Peli,

Thanks for the response. I'm embarrassed to admit this, but the real problem was a simple coding error. I'm using a bare-metal firmware project from an Altera training class as my starting point. I added a simple memory test at the end of main, but what I didn't realize was the last function call before my memory test, uninitialized all the bridges and put them back into reset. Once I moved my memory test before the code that reset the bridges, it worked as I expected. Something I was not able to fully understand, was the mapping of the bridges. When I first had problems, I thought it might be that I had to set some bits in the l3 remap register to map the bridges into the ARM's memory space. In the end this was not necessary. I'm not sure why? Maybe these bits are set in the preloader or in the bridge initialization functions, but I didn't see any code in either of these to indicate where this may be happening. Something is missing from my understanding of the remap register and how it is used to configure the h2f bridges.

Peli, I appreciate what you shared, because it shows me a better method for assigning base addresses. My background is hardware, so I'm a bit of hack when it comes to firmware.

Thanks,

-kstolp

Hi

I Would appreciate it if someone can guide me how to read and write to a on chip memory connected to the H2F Bridge (Full) BAREMETAL. I do the following

while (1==1)

{

alt_write_word ((0xc0000000 + TEST_ONCHIP_MEMORY_BASE+loop), ~loop);

ReadValue = alt_read_word (0xC0000000 + TEST_ONCHIP_MEMORY_BASE+loop);

ReadValue = alt_read_word (0xC0000000 + TESTFIFO_RD_BASE+loop);

ReadValue = alt_read_word (0xC0000000 + TESTFIFO_STATUS_BASE+loop);

loop++;

}

The On chip memory, TESTFIFO RD and TESTFIFO Status is all conencted to h2F bridge.

I can read successful from on chip memory with offset 0. But when reading from TESTFIFO_RD and TESTFIFO_STATS i read 0xffffffff, the inverted of loop (0x0). So i read the same value for all 3 ports.

Also when the while loop re-execute the second time e.g. loop = 1, the software crash when writing to the on chip memory.

To initialize the H2F Bridge i use the Altera library in alt_address_space.h & alt_bridge_manager.h as follows

status = alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM,

ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM,

ALT_ADDR_SPACE_H2F_ACCESSIBLE,

ALT_ADDR_SPACE_LWH2F_ACCESSIBLE);

}

if (status == ALT_E_SUCCESS)

{

// STEP 12: Attempt to initialize bridge

status = alt_bridge_init(bridge, NULL, NULL);

// status = alt_bridge_init(ALT_BRIDGE_F2H, NULL, NULL);

status = alt_bridge_init(ALT_BRIDGE_H2F, NULL, NULL);

// status = alt_bridge_init(ALT_BRIDGE_LWH2F, NULL, NULL);

}

I have a baremetal program working, preloader / spl, u boot and LW Bridge all is working 100%.

Thanks

Can you please share me the Lab1b-HWLibs bare-metal example?

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Has anyone been able to use the HPS2FPGA AXI Bridge to access an avalon-mm slave in the FPGA fabric. The Cyclone V SoC Kit's Golden Hardware Reference Design (GHRD) connects an on-chip ram to the hps2fpga bridge, but I have not come across any software examples that access this on-chip memory. I am using the Lab1b-HWLibs bare-metal example from Altera's "Developing Software for ARM SoC FPGA" training, as a starting point to create my own bare-metal firmware project. I am trying to add to this project code to access the on-chip ram connected to hps2fpga bridge. From looking at the memory map views in Altera's documentation, I don't think the default MPU memory map allows the MPU to access the hps2fpga bridge. What I also get from the documentation is the hps2fpga bridge is enabled by setting bit 3, in the l3 remap register. I tried using the following lines of code to do this:

uint32_t remap_mask = ALT_L3_REMAP_H2F_SET_MSK;

alt_setbits_word(ALT_L3_REMAP_ADDR, remap_mask);

I have also tried using the DS-5 Debugger Registers tab to write an 8 (i.e. set bit 3) to the l3 remap register. Neither of these has worked. When I try to access the memory using the 0xC000_0000 offset shown in Altera's documentation, it hangs the MPU. This is true whether I try to access the memory with c-code or use the debugger to read the memory.

Any insight is appreciated.

Thanks,

-kstolp

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