Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Cyclone V SoC HPS2FPGA AXI Master - How to enable?

Has anyone been able to use the HPS2FPGA AXI Bridge to access an avalon-mm slave in the FPGA fabric. The Cyclone V SoC Kit's Golden Hardware Reference Design (GHRD) connects an on-chip ram to the hps...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

if using a bare-metal project, initial the h2f axi bridge is necessary, if your mem test code is put after the reset, the bridge is not worked, so you need to re-initial it. the initial program is included in the bare-metal program too. but not need your manual remap it to the ARM's memory space, what i shared is under OS, only under OS, you should remap the component's address space. you can refer to the DS-5 example project "Altera-SoCFPGA-HardwareLib-GNU" for more detail.