Cyclone V SoC HPS2FPGA AXI Master - How to enable?

Peli,

Thanks for the response. I'm embarrassed to admit this, but the real problem was a simple coding error. I'm using a bare-metal firmware project from an Altera training class as my starting point. I added a simple memory test at the end of main, but what I didn't realize was the last function call before my memory test, uninitialized all the bridges and put them back into reset. Once I moved my memory test before the code that reset the bridges, it worked as I expected. Something I was not able to fully understand, was the mapping of the bridges. When I first had problems, I thought it might be that I had to set some bits in the l3 remap register to map the bridges into the ARM's memory space. In the end this was not necessary. I'm not sure why? Maybe these bits are set in the preloader or in the bridge initialization functions, but I didn't see any code in either of these to indicate where this may be happening. Something is missing from my understanding of the remap register and how it is used to configure the h2f bridges.

Peli, I appreciate what you shared, because it shows me a better method for assigning base addresses. My background is hardware, so I'm a bit of hack when it comes to firmware.

Thanks,

-kstolp