Cyclone V SoC Dev Kit PCIe End Port Example

Hi kstolp,

The example designs with the "Qsys PCIe core fails timing" thread used the PCIe Hard IP clock to clock the Qsys system primarily because that was how the first few examples I looked at implemented a simple design. In general I would not recommend doing this, but would instead use a local clock source, eg., a 100MHz Qsys clock should be fine. This allows you to implement a JTAG-to-Avalon-MM bridge into your Qsys system that will work regardless of the state of the PCIe clock.

The approach you are taking should work just fine, and would be the recommended approach.

There's a couple of things you can do;

1. Use a PCIe logic analyzer to trace the traffic that occurs when the system works and when it does not.

2. Use the SignalTap II logic analyzer to trace the traffic (if you do not have access to a PCIe analyzer)

3. Create a simulation and look to see whether you can "boot" your system, eg., enumerate the PCIe end-point and then access your Qsys system.

I'd recommend having (3) regardless of whether you do (1) or (2) as it forces you to really understand what needs to occur to get your system up-and-running. Once you have traces from (1) or (2), you can update your simulation to implement the same access sequence (eg., redundant accesses performed by the root-complex).

Cheers,

Dave