Cyclone V SoC Dev Kit PCIe End Port Example

Dave,

From the thread you posted above, you did some PCIe Hard IP compilation tests and had some issues with Altera's examples meeting timing. As mentioned in one of my previous posts to this thread, I've had some difficulty with the PCIe Hard IP meeting timing when targeting the FPGA on the Cyclone V SoC dev kit board. The main issue is the application layer clock has to be 125 MHz and the avalon switch fabric generated by Qsys can't really run at this clock speed unless the interconnects are kept to a minimum. The Altera example is a good starting point, but now I want to add some other components which will increase the number of avalon interconnects that need to run at 125 MHz. In fact, when I do this, it becomes impossible to meet the 125 MHz timing requirement.

My initial fix for this issue was to add clock bridges between all of the PCIe hard IP application layer interfaces and all the other avalon-mm components. This keeps the interconnect logic running at 125 MHz to a bare minimum. I chose to run the rest of the interconnect fabric at 50 MHz, which is an easy timing requirement to meet, no matter how complex my interconnect logic becomes. This solution seemed to be working fine, but today I encountered a problem. The PC I've been using works fine with my bridged design, but the PC we are using to develop the device driver on, does not recognize the board when my bridged design is loaded in the FPGA. Looking at the device manager (Windows 7), the PCIe root node connected the C5 SoC dev kit board, is unhappy. If I reload Altera's original example, both PC's recognize the board.

Is there a problem with my clock bridged approach? Any other thoughts as to what may be my problem?

Thanks,

kstolp