Cyclone V SoC Dev Kit PCIe End Port Example

So here is a couple more things I've learned:

1. I was able to get the example end port design to meet timing with the "8ES" part number, by setting the routing timing optimization setting to "Maximum" in the more fitter settings window. If you make a new project from scratch, make sure to use the qsys and quartus settings found in Altera's example. These settings optimize for clock speed, which you need if you want to meet the 125 MHz requirement for coreclkout.

2. Don't allow your BAR address space to become larger than 28-bits. This caused my PC not to boot, which took me a lot of time and frustration to figure out. Dave pointed this limitation out in an old thread titled "PCIe BAR size limitations in Qsys"