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The Cyclone V SoC dev kit board has a PCIe clock generator device made by Silicon Labs. This clock generator has two differential 100 MHz clock outputs. One output is attached thru zero ohm resistors to the backplane connector and one is routed to the FPGA where it is used as the reference clock input to the PCIe high-speed transceivers. I removed the resistors that go from the clock generator to the backplane, since the pc motherboard also drives the PCIe REFCLK. So I don't think this is the problem and I don't think PCIe requires that the 100 MHz REFCLK come from the backplane. In fact Altera gives you the option to use a 125 MHz reference clock.
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PCIe in a motherboard expects a reference clock that is synchronous at all boards. That is why the SoC kit is supplying a reference clock to both the Cyclone V and the PCIe connector - because the device needs to see a synchronous reference clock.
Your setup needs to figure out a way to route the reference clock being driven onto the PCIe connector over to the FPGA. I'd recommend removing both 0-ohm resistors from the SiLabs part, and jumpering the PCIe clock coming into the connector, over to the resistor that drives the FPGA REFCLK pin.
Probe the pins with a scope to check that the differential clock at the FPGA looks clean.
Cheers,
Dave
Honored Contributor
