Cyclone V SoC Dev Kit PCIe End Port Example

The Cyclone V SoC dev kit board has a PCIe clock generator device made by Silicon Labs. This clock generator has two differential 100 MHz clock outputs. One output is attached thru zero ohm resistors to the backplane connector and one is routed to the FPGA where it is used as the reference clock input to the PCIe high-speed transceivers. I removed the resistors that go from the clock generator to the backplane, since the pc motherboard also drives the PCIe REFCLK. So I don't think this is the problem and I don't think PCIe requires that the 100 MHz REFCLK come from the backplane. In fact Altera gives you the option to use a 125 MHz reference clock.