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BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
4 months ago

Cyclone V SoC custom board preloader boot sdram test issue

Dear Intel FAE and ALL, This is Brian and having issue on maximum 2GB DDR3 boot sanity test. There is a warning like these: "SDRAM: Running EMIF Diagnostic Test ...Iteration 1734:, expect 0x20a6...
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tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi


Apologize for the late reply.

For the new flow the SPL s no longer generated from the bsp-editor.

The SPL version is tied together with the u-boot version.

It is still separate from the uboot. ( https://github.com/altera-fpga/u-boot-socfpga/blob/socfpga_v2024.07/arch/arm/mach-socfpga/spl_gen5.c)

In the latest spl code, there is no longer sdram diagnostic test.


New flow:

https://altera-fpga.github.io/rel-25.1.1/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/#the-new-flow


Regards

Jingyang, Teh


  • BrianSune_Froum's avatar
    BrianSune_Froum
    Icon for Contributor rankContributor
    3 months ago

    @JingyangTeh_Altera

    Allow me, based on my ultra lite knowledge on U-Boot and SPL.

    The DDR_SI test actually can be transferred from old U-Boot to latest mainstream Das U-Boot (Altera U-Boot).

    According to Siemens patches I do see s.t. very similar.

    This is just feature that Altera plan to do so or not.

    Apart from U-Boot version I cannot see such test is very complex compared to old 2013 trunk.

    Meanwhile, the U-Boot itself from mainstream already included calibration of SDRAM, but had not study deep on such test.