Cyclone V SE Signaltap pin placement

Hi all,

I've been trying to add a Signal Tap instance to my design on a Cyclone V SE (5CSEMA4U23C6) using Quartus Prime 18.0/18.1. I setup the Signal Tap using Tools -> Signal Tap Logic Analyzer and enabled it in Assignments -> Settings.

However the fitter says it couldn't fit the design with the following error messages:

		Error (16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:
			Error (169057): Can't place I/O pin altera_reserved_tck at pin location AB5 -- I/O pin uses weak pullup, which is not supported by this pin location (1 location affected)
				Info (175029): PIN_AB5
	Error (175019): Illegal constraint of I/O pad to the location PIN_Y9
		Info (14596): Information about the failing component(s):
			Info (175028): The I/O pad name(s): altera_reserved_tdo
		Error (16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:
			Error (169057): Can't place I/O pin altera_reserved_tdo at pin location Y9 -- I/O pin uses weak pullup, which is not supported by this pin location (1 location affected)
				Info (175029): PIN_Y9

If I disable the Signal Tap instance, the design compiles fine without the above errors. I've tried poking around in the pin planner and assignment editor, but these two pins are reserved from editing.

Does anyone have any clue on what I can do to solve this problem?