AJienNew Contributor7 years agoCyclone V SE Signaltap pin placement Hi all, I've been trying to add a Signal Tap instance to my design on a Cyclone V SE (5CSEMA4U23C6) using Quartus Prime 18.0/18.1. I setup the Signal Tap using Tools -> Signal Tap Logic Analyzer an...Show More
Rahul_S_Intel1Frequent Contributor7 years agoHi , Can you please remove the JTAG pins and keep other pins in signal tap and test
Recent DiscussionsVcm for the clock input pins of agilex5 E-series FPGA A5ED065BB32AE5SR0Arria 10: Remote Update Factory Fallback won't work & Watchdog does not triggerIBIS models GTS banks agilex 5EClarification on Arria 10 Design Security Featuresrsu_client failing to write to slot