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Altera_Forum's avatar
Altera_Forum
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9 years ago

Cyclone V: LVDS I/O restrictions and differential pad placement rules

Hi All!

I've a problem with my Cyclone V 5CEBA7F23C7N. I had to use 12 pairs of RX LVDS I/O pins and 12 pairs of TX LVDS I/O pins in no more than two FPGA banks. I read the section called "Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement Rules" in Cyclone V Device Handbook and I understand that single-ended pins cannot be placed next to a LVDS pin. But unfortunately, it's not clear if LVDS signals can be placed in adjacent pins. Since I have a lot of LVDS signals and I wish to occupy only two banks, this information is critical.

Could anyone help me please?

Thanks,

Francesco

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Hi,

    In differential pad placement mapping file you can find that only single ended LVTTL, LVCMOS, and un-terminated HSTL/SSTL signals must not be placed in the keep out zones. So in my undertanding this means that you can place LVDS and other terminated pins next to the adjecent LVDS pins. I have used LVDS placed next to each other and design worked with no problems.