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Altera_Forum
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9 years ago

Cyclone V: LVDS I/O restrictions and differential pad placement rules

Hi All! I've a problem with my Cyclone V 5CEBA7F23C7N. I had to use 12 pairs of RX LVDS I/O pins and 12 pairs of TX LVDS I/O pins in no more than two FPGA banks. I read the section called "Guideli...
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Altera_Forum
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9 years ago

Hi,

In differential pad placement mapping file you can find that only single ended LVTTL, LVCMOS, and un-terminated HSTL/SSTL signals must not be placed in the keep out zones. So in my undertanding this means that you can place LVDS and other terminated pins next to the adjecent LVDS pins. I have used LVDS placed next to each other and design worked with no problems.