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John_C's avatar
John_C
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7 months ago
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Cyclone V HMC IBIS Model

I cannot find the IBIS model for the Cyclone V HMC (Hard memory controller). I tried looking here https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html but these models appear to only contain the general purpose FPGA fabric I/O models. Where can I find the HPS DDR IBIS file?

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  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    6 months ago

    Hi John_C,


    I think you should follow the IO standard that the IP is currently using to connect the memory component.

    For example DDR3, the IO standard is SSTL-15. You can use SSTL15_<io>_<feature> or similar IBIS model.



    Regards,

    Adzim


3 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi John_C,


    I think you should follow the IO standard that the IP is currently using to connect the memory component.

    For example DDR3, the IO standard is SSTL-15. You can use SSTL15_<io>_<feature> or similar IBIS model.



    Regards,

    Adzim


    • John_C's avatar
      John_C
      Icon for New Contributor rankNew Contributor
      6 months ago

      This is what I had ended up using. Thank you.

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    6 months ago

    Hi John_C,


    Do you have any further questions or feedback in this forum?


    Regards,

    Adzim