Forum Discussion

jkhoo's avatar
jkhoo
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Cyclone V GX starter Kit : XCVR_LOOPBACK_TEST clocking from REFCLK_p0 to PLL Reconfig inside xcvr ip

Hi Intel team, In the C5G_HSMC_XCVR_LOOPBACK_TEST project, clock generator si5338 CLK1A (U20.Pin18) with default frequency of 125Mhz is connected to REFCLK_p0. And REFCLK_p0 is routed to hsmc_xc...
Other Ips
jkhoo's avatar
jkhoo
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi Zi Ying,

Can it concluded that :-

  • the ref_clk in C5_HSMC_XCVR.qsys is wrongly set to 644.53Mhz and
  • PLL reconfiguration reference clock freq is wrongly set to 100Mhz.

And i should set them to 125Mhz.

Regards, JJ