Cyclone V GX starter Kit : XCVR_LOOPBACK_TEST clocking from REFCLK_p0 to PLL Reconfig inside xcvr ip

Hi Intel team, In the C5G_HSMC_XCVR_LOOPBACK_TEST project, clock generator si5338 CLK1A (U20.Pin18) with default frequency of 125Mhz is connected to REFCLK_p0. And REFCLK_p0 is routed to hsmc_xc...