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Altera_Forum
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10 years ago

Cyclone V GX FPGA PLL not working

I have used the Cyclone V GX C7 device(5CGXFC7C7F23C8) in my design. I do not use the Gbit transceiver in my design, so I have not get the relevant power pins like VCCE_GXBL VCCL_GXBL and VCCH_GXBL connected . I tried to use the PLL in my design and found the PLL do not work. I check the power supply for the PLL, like the VCCA_FPLL and VCC_AUX is connected to 2.5 V LDO output, which looks fine. The clock is provided from high quality clock source and should also be fine. The only clue is from the 'Cyclone V Device Family Pin Connection Guidelines' which says the VCCL_GXBL functions Clock network power, specific tothe left (L) side of the device. I then tried to provide clk[5]_p pin with a single_ended LVCMOS clock(PLL is set to work with 100 MHz input, 40 MHz, 160 MHz output) and the used Fractional PLL is X89_Y1 and all of them are located on the right side of the chip, but the PLL still did not give the output. I want to check if the above mentioned Gbit Transceiver related power pins must be connected to get the clock network and the PLL to work? Or if it is possible to get the current PCB board to work if I replace the GX series device with an E series device with compatible pin map (5CGXFC7C7F23C8 --> 5CEFA7F23C8) but without Gbit transceivers?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks for your reply! As I mentioned in my first message, is it possible to make it work if I replace the current FPGA with a pin compatible E series FPGA? I check the pin map for the corresponding E series FPGA, the VCCH_GXBL is used as VCCA_PLL. It looks like part of the VCCA_PLL power pins are not connected, will the other half of the PLLs work for a E series FPGA?

    --- Quote Start ---

    You may refer to PCG-01014-2.1 Cyclone® V Device Family Pin Connection Guidelines. According to the description, "VCCH_GXBL and VCCA_FPLL must always be powered up for the PLL operation."

    https://www.altera.com/literature/dp/cyclone-v/pcg-01014.pdf

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Refer to the 'power management' section, chapter 10, of the 'cyclone v device handbook (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf)'. Refer to Table 10-2. Providing the monitored rails are powered, the device will exit POR, allowing you to use the device. VCCA_FPLL falls into the 'Not Monitored' category. So, assuming the monitored rails are powered correctly, at least your device should exit POR.

    However, I wouldn't rely on your PLLs working if you do not have all the VCCA_FPLL pins powered - it looks like you're missing power to two out of 6 VCCA_FPLL pins. Whilst some devices may power half the PLLs from half the PLL power pins, the Cyclone V documentation doesn't state whether that's the case for this family. I suspect it's more likely that the 6 power pins are connected together in the package - although I can't state that is the case. So, power to 4 might/could be enough to get it working.

    You'll just have to try it. However, I think you may end up having to re-spin the board. I wouldn't consider shipping a unit without the FPGA being powered correctly, even if your re-worked board does appear to work.

    Cheers,

    Alex