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Altera_Forum
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8 years ago

Cyclone V Fractional PLLs don't output expected clock frequency

I'm using Quartus 17.0.2. I have trying to generate a 148.5MHz clock with a 50MHz input reference clock. When I put the PLL in fractional mode and enter 148.5M as my target frequency the megawizard s...
Altera_Forum's avatar
Altera_Forum
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8 years ago

So I entered the physical parameters manually and it said it could achieve a frequency of 148.4999999MHz. I'm fine with that.

So I tried to synthesize the design and I am getting an absolutely bizarre synthesis error: 

Error (13305): Verilog HDL error at altera_pll.v(2163): can't find port "refiqclk_1" File: c:/altera/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 2163

This isn't even one of my source files!! O.o

I have attached the file that the megawizard generated. I'm not sure what else to say...how can I compete with source files errors in Quartus' own installation directory..........?????