New ContributorHi ,
We are using Cyclone V (5CEBA9F23C7) FPGAs In our custom boards .We are using the built in PLL ip for generating clocks required for applications .
In one such board the FPGA PLL is not locking ('locked' signal in PLL ip is low). Inputs to the PLL (clock and reset) are found to be good .
Same image works in other boards we're not observing PLL issue .
What are the ways to debug this issue further ?
Regular ContributorHi,
Have you check the VCCA_FPLL for that particular board if they are supplying stable power? This could be the reason for the PLL not locking.
Regards,
Aqid
Regular ContributorHi,
Do you need more support on this issue?
Regards,
Aqid
Regular ContributorAs we do not receive any response from you on the previous reply have been provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you by replying to this thread.
