metaprogrammer
New Contributor
New ContributorCyclone V f2sdram bridge clock rate
I could not find it in the datasheet - is it possible at all to drive f2sdram bridge in Cyclone V devices at a clock rate more than 100MHz?
Forum Discussion
1 Reply
EBERLAZARE_I_IntelRegular Contributor
Hi,
It is possible, but at higher clock rates, a PLL is necessary to ensure that the SDRAM clock toggles only when signals are stable on the pins.
More info could be found here:
https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/nios2/n2cpu_nii51005.pdf#page=3
Regards.
