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Altera_Forum
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10 years ago

Cyclone V DDR3L & 1.35V I/O

My platform is Cyclone V SX series FPGA with DDR3L for HPS and for FPGA. Problem: DDR3L is 1.35V. I need to use SSTL-135 for the FPGA banks with DDR3. Also I want to use free pins of the same ba...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If your input signals "are very slow" then yes, you can just treat the SSTL-135 input pins in a LVCMOS like manner. If you have the option of siting a parallel termination resistor then it's good practice do that too, although you shouldn't need to fit it to do what you're proposing.

Cheers,

Alex