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Altera_Forum's avatar
Altera_Forum
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10 years ago

Cyclone V DDR3L & 1.35V I/O

My platform is Cyclone V SX series FPGA with DDR3L for HPS and for FPGA.

Problem:

DDR3L is 1.35V. I need to use SSTL-135 for the FPGA banks with DDR3. Also I want to use free pins of the same banks as GPIO.

If I change the type of DDR3 from 1.35V to 1.5V there's no problem to use 1.5V I/O standard. But if memory is 1.35V there is no standard for 1.35V I/O (except SSTL-135).

I tried to use 1.2V and 1.5V I/O standard. Both of them give error in fitter.

Question:

Can I generate project in Quartus for 1.5V memory and use GPIO as 1.5V I/O standard, but in hardware use 1.35V?

May be there are some different methods?

Thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If the actual voltage supply in hardware is lower than the required, you should expect that the IO performance might be out from the specs.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If you're using DDR3L then I recommend you leave the settings for the bank it uses at 1.35V. I don't recommend you specify 1.5V for the memory interface and then power it at 1.35V.

    If you need additional user GPIO in the same bank then you should be able to specify it's I/O standard as SSTL-135. If Quartus doesn't allow you to do that then it may well have limitations on the use of other pins in a bank used for DDR. If this is the case then, depending on the error given, you could try adding an 'IO_MAXIMUM_TOGGLE_RATE' constraint to your GPIO. That may allow Quartus to find a fit. Try that and, if necessary, post the errors you get.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If I use SSTL-135, then I have error described in https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01292013_881.html. This link also has workaround/fix for this problem.

    Using this fix everything OK. But now one more question about SSTL-135. My signals are very slow, this means I don't need to terminate them at the both sides. So if I don't use input parallel termination will I have voltage range of a signal from 0 to 1.35V (like LVCMOS)?

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If you do not have termination, then it might violtate the SSTL IO standard requirement. You might not be able to use with other SSTL-135 compatible device.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If your input signals "are very slow" then yes, you can just treat the SSTL-135 input pins in a LVCMOS like manner. If you have the option of siting a parallel termination resistor then it's good practice do that too, although you shouldn't need to fit it to do what you're proposing.

    Cheers,

    Alex