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Altera_Forum
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10 years ago

Cyclone V DDR3L & 1.35V I/O

My platform is Cyclone V SX series FPGA with DDR3L for HPS and for FPGA. Problem: DDR3L is 1.35V. I need to use SSTL-135 for the FPGA banks with DDR3. Also I want to use free pins of the same ba...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If you're using DDR3L then I recommend you leave the settings for the bank it uses at 1.35V. I don't recommend you specify 1.5V for the memory interface and then power it at 1.35V.

If you need additional user GPIO in the same bank then you should be able to specify it's I/O standard as SSTL-135. If Quartus doesn't allow you to do that then it may well have limitations on the use of other pins in a bank used for DDR. If this is the case then, depending on the error given, you could try adding an 'IO_MAXIMUM_TOGGLE_RATE' constraint to your GPIO. That may allow Quartus to find a fit. Try that and, if necessary, post the errors you get.

Cheers,

Alex