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Altera_Forum
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10 years ago

Cyclone V DDR3L & 1.35V I/O

My platform is Cyclone V SX series FPGA with DDR3L for HPS and for FPGA. Problem: DDR3L is 1.35V. I need to use SSTL-135 for the FPGA banks with DDR3. Also I want to use free pins of the same ba...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If I use SSTL-135, then I have error described in https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01292013_881.html. This link also has workaround/fix for this problem.

Using this fix everything OK. But now one more question about SSTL-135. My signals are very slow, this means I don't need to terminate them at the both sides. So if I don't use input parallel termination will I have voltage range of a signal from 0 to 1.35V (like LVCMOS)?

Thanks.