Forum Discussion
Lukas187
New Contributor
4 years agoHi.
I did find my timing issue. Pretty wired but simple if you read the right documents. I can recommend "AN 822: Intel® FPGA Configuration
Device Migration Guideline".
There you should check the tDH (data hold timing). The clock line has to be absurdly long, or the clock has to be delayed in another way.
Lukas