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Altera_Forum
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10 years ago

Cyclone V and Gate Level Simulation

Quartus won't run a gate level simulation when using the Cyclone V family. Is it possible to run gate level simulation with the Cyclone V devices? For other devices, Quartus generates simu...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Static timing analysis alone does not allow for comprehensive verification. Among the issues

- STA cannot identify asynchronous interfaces

- The error prone selection of false paths

- Constraint requirements for multi-cycle paths

- Common concurrence point along implementation flow to a known good test bench is lost.