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Altera_Forum
Honored Contributor
Honored ContributorCyclone V and Gate Level Simulation
Quartus won't run a gate level simulation when using the Cyclone V family.
Is it possible to run gate level simulation with the Cyclone V devices? For other devices, Quartus generates simulation files: up_counter.vo up_counter_6_1200mv_0c_slow.vo up_counter_6_1200mv_85c_slow.vo up_counter_min_1200mv_0c_fast.vo But with the Cyclone V family it is only generating: up_counter.vo8 Replies
Altera_ForumStatic timing analysis alone does not allow for comprehensive verification. Among the issues
- STA cannot identify asynchronous interfaces - The error prone selection of false paths - Constraint requirements for multi-cycle paths - Common concurrence point along implementation flow to a known good test bench is lost.- Altera_Forum
Cyclone V = no gate level simulation
Rely on TimeQuest - Altera_Forum--- Quote Start --- Cyclone V = no gate level simulation Rely on TimeQuest --- Quote End --- Thanks. Is there a reason that gate level is not supported?
- Altera_Forum--- Quote Start --- Cyclone V = no gate level simulation Rely on TimeQuest --- Quote End --- Good info sharing. Dint aware of it till now.
- Altera_Forum
Reason is money, models for gate level simulation are $$$ and 28nm design is already $$$
- Altera_Forum
you are right, think it is a way to save $$.
- Altera_Forum
I'd bet that Altera decided that Timequest was more accurate than gate level simulation so there was no reason to support both methods.
- Altera_Forum
You are right. Also the CV should be of the low cost FPGA series.
