Honored ContributorQuartus won't run a gate level simulation when using the Cyclone V family.
Is it possible to run gate level simulation with the Cyclone V devices? For other devices, Quartus generates simulation files: up_counter.vo up_counter_6_1200mv_0c_slow.vo up_counter_6_1200mv_85c_slow.vo up_counter_min_1200mv_0c_fast.vo But with the Cyclone V family it is only generating: up_counter.vo
Honored ContributorStatic timing analysis alone does not allow for comprehensive verification. Among the issues
- STA cannot identify asynchronous interfaces - The error prone selection of false paths - Constraint requirements for multi-cycle paths - Common concurrence point along implementation flow to a known good test bench is lost.Honored ContributorCyclone V = no gate level simulation
Rely on TimeQuestHonored ContributorHonored ContributorHonored ContributorReason is money, models for gate level simulation are $$$ and 28nm design is already $$$
Honored Contributoryou are right, think it is a way to save $$.
Honored ContributorI'd bet that Altera decided that Timequest was more accurate than gate level simulation so there was no reason to support both methods.
Honored ContributorYou are right. Also the CV should be of the low cost FPGA series.
