Cyclone V ALTLVDS_RX output clock at half the expected rate

Yeah, I'm thinking I'm going to have to switch to using an external PLL so I have more control over the clocks. I just assumed the input clock rate didn't really matter as long as it was related to the data rate. In other words I assumed the ALTLVDS block would use the input clock to generate the data rate clock and then based on the deserialization factor it would use the data rate clock to create the output clock. However, if the internal data rate clock is running at half rate (because maybe it is DDR) then dividing it by the deserialization factor would create a clock at half the output (parallel) data rate. What concerns me then is that if the output register is turned on in the megafunction (I think there is an option for registering the output data with rx_outclock) then the module would be throwing away half the data unless that register was a Double data rate register also.