Cyclone V ALTLVDS_RX clocking

Hi again,

I just wanted to share my experience in case someone else needs it.

For the last days I have been trying to understand which lvds channels can I drive with each corner fractional PLL and this is the conclusion I could get:

- A corner fractional PLL can drive any of the LVDS channels of just one of its corner edges.

As an example, the bottom-right corner FPLL can drive any LVDS channel of the FPGA bottom edge or the FPGA right edge but not LVDS channels of the FPGA bottom edge and right edge at the same time.

For the different compilations I have carried out this rule seems to be right. I could not find any performance issue due to the usage of LVDS channels from different I/O banks within the same edge.

In any case, I think this is some information Altera could provide in the FPGA documentation.

Cheers!!