Altera_Forum
Honored Contributor
10 years agoCyclone V active serial configuration w/ EPCS128 failure.
Hi all,
I have run in to an issue on my custom board that I can't seem to figure out. - The board has an active serial configuration setup. The EPCS128 is programmed by an external programmer and then put into a socket on the board. - The configuration cycle starts (I can see it on the scope), and I can see the FPGA send the read status command and get it back, and send the read device ID and get it back. - The FPGA then initiates a fast read of the EPCS and I can see the data beginning to stream. The problem occurs when the FPGA deasserts nCS before all the data is done being streamed, which causes nSTATUS to detect an error, which causes it to pulse low, which restarts the configuration cycle. Some other info. I am using ASx1. DCLK is 12.5 MHz. All voltages are at 3.3V for configuration. I am using Quartus II v15.0. The external programmer I am using is a ChipProg481. This was meant to be a stand alone board so there is no usb-blaster header on to try program that way. DCLK has some high frequency ringing, but nothing that causes a dip below 3V and a rise above 0.3V, so well within the spec of both devices. Has anyone encountered a similar issue. Any help is appreciated. Thanks,