Occasional ContributorCyclone V (5CGTFD9) 4X PCIe Connections for Data Lines and RefClk
I need some guidance on properly connecting PCIe interface to the XCVR banks on a Cyclone V D9 (12 XCVR channels) to get PCIe Gen2 X4 (5Gbps) signaling to work correctly. I copied the C5 DVK layout, but am only getting 2.5 Gbps rates and only 1-2X lanes are connecting.
The C5 datasheet (cv_5v3-683586-670578) for XCVRs for this device in Figure 1-5 describes the XCVR configuration for our Cyclone V chip (a GT device with 12 XCVR channels). It says that Ch1-2 in both GXB_L0 and GXB_L2 are the "PCIe Hard IP" regions. However, the C5 DVK schematic (which I copied for our design), shows the PCIe signals connected to GXB_L0/L1 Channels 0-3. Channels 0 and 3 are not part of the PCIe Hard IP. Consequently, there appears to be a conflict between how the DVK PCIe lines are connected vs the recommended connection guidelines from the datasheet. Please clarify the proper connections to realize a PCIe 4X Gen2 (5Gbps).
Another question that I have is what is the best reference clock input to enable our 4X 5Gbps configuration? The C5 DVK has the PCIe RefClk pair coming into REFCLK1L (pins W11/V10). Should this be connected to REFCLK0L (pins AA11/AB10)?
The "Configuration via Protocol (CvP) datasheet (ug_cvp-683889-666868) states in Notes 2 & 3 of Figure 1-1:
2. PCIe Hard IP block (bottom left) for CvP and other PCIe applications.
3. PCIe Hard IP block only for PCIe applications and cannot be used for CvP.
