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ToddW's avatar
ToddW
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Cyclone V (5CGTFD9) 4X PCIe Connections for Data Lines and RefClk

I need some guidance on properly connecting PCIe interface to the XCVR banks on a Cyclone V D9 (12 XCVR channels) to get PCIe Gen2 X4 (5Gbps) signaling to work correctly. I copied the C5 DVK layout,...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi @ToddW,


Are you referring to the Cyclone V GT dev kit?

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.html


According to Figure 1-5 in Cyclone V Device Handbook Volume 2: Transceivers (ug-cv_5v3-683586-670578), the PCIe Hard IP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 1 and Ch 2 of bank GXB_L2. This means the PCIe Hard IP block is located near the mentioned channels. It does not mean that the PCIe Hard IP cannot use channels such as 0 and 3.


Please connect the input reference clock to pin W11 (PCIE_REFCLK_P) and V10 (PCIE_REFCLK_N). Ensure that the DIP switches on the dev kit are set to default positions following Section 4.2: https://www.intel.com/content/www/us/en/docs/programmable/792833/current/factory-default-switch-and-jumper-settings.html


You may try the Cyclone V PCIe Gen 2.0 x4 design from the FPGA Design Store and refer to the QSF for the pin assignments of PCIe signals. It works for the Cyclone® V GT FPGA Development Kit DK-DEV-5CGTD9N to bring up the Gen2 x4 configuration:

https://www.intel.com/content/www/us/en/design-example/749022/cyclone-v-fpga-pcie-2-0-x4-avalon-memory-mapped-dma-design-example.html


Thanks.

Best Regards,

Ven