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Altera_Forum
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12 years agoHow are you connecting up the buffer - schematically? VHDL? Verilog? Quartus is not happy with the way in which you've instantiated it.
Post some code to help us help you Regards, AlexHow are you connecting up the buffer - schematically? VHDL? Verilog? Quartus is not happy with the way in which you've instantiated it.
Post some code to help us help you Regards, Alex