Hello, I am currently trying to find out how to trigger a transfer of DMA Controller Intel FPGA IP (connected between f2h_sdram0 and on-chip 2-port RAM in QSYS) using an interrupt from the FPGA side. The DMA works when the transfer is started from the Linux userspace by writing GO bit (2^3) to the CONTROL register (offset 6 in the /dev/mem memory-mapped space of the controller's control_port_slave on the AXI bus). The CONTROL register contains interrupt enable bit (2^4) but I believe it is only used to enable Interrupt Sender (irq port of the IP block). Q: Is this IP related to the HPS' DMA Peripheral Requests (0 to 7)? If so, how to tell the IP block what request should be used as an interrupt source for trigger? Or maybe I use wrong IP block and I should use eg. mSGDMA instead? Thanks in advance.

Hi,These are the interfaces, you need to refer to the Cyclone V HPS TRM, f2h interrupts:https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/interrupts-38262.htmlDMA controller interface:https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/dma-controller-interface-83696.htmlAlternatively, you may want to look at an example design below from Robertofem:https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-applications/DMA_transfer_FPGA_DMAC

Hi, thanks, I have already seen these resources before. In the first site there is no information about using f2h interrupts directly with the DMA Controller. Of course I could use an interrupt kernel driver writing the DMA control register but that's not what I am looking for. The second link you provided also doesn't explain how to connect the DMA Peripheral Requests (f2h_dma_reqX) to the DMA Controller QSYS. It also doesn't say how the DMA controller in the HPS is related to the QSYS component. The third link provides source code (fpga_dmac_api.c) I have been already using (ie. the CONTROL register I mentioned in the first post). But it also doesn't relate to the interrupts or to triggering of the DMA from the FPGA side. The only way I can think of right now is accessing the control_port_slave (Avalon MM Slave) of the DMA Controller QSYS component directly from the fabric but it would mean sharing the physical address of the allocated buffer from HPS first, which doesn't seem like a valid approach to me. What's the proper way to accomplish this?

Hi,We do not really have a direct example for this, but to best guide you, it is the peripheral requests mentioned for DMA controller for Cyclone V SoC:https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/peripheral-request-interface-mapping.htmlThe FPGA peripherals, these channels are mapped in the registers of Cyclone V SoC here:https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410067855000.htmlFor future usage and info on the DMA controller, you need to refer to the ARM doc , on the "using events and interrupts" section:https://developer.arm.com/documentation/ddi0424/b/functional-overview/using-events-and-interrupts/using-an-event-to-restart-dma-channelsFrom there you can either use an event to restart the DMA channels or Interrupting a microprocessor. I hope these documents may help you.

Hi,Do you have any other questions that I may help with?

Hello, thank you for the provided links. I started digging deeper into the register map of the Cyclone V HPS and into the ARM Docs to find answers to my questions about usage of the AMBA DMA Controller DMA-330. As far as I understand it now, the registers mentioned in the DMA Module Address Map are all read-only except the Debug registers (DBGCMD Debug Command Register, DBGINST0 Debug Instruction-0 Register, DBGINST1 Debug Instruction-1 Register), the 2 interrupt-related Control registers (INTEN Interrupt Enable Register, INTCLR Interrupt Clear Register) and the WD Watchdog Register in Configuration registers, so the DMAC can be controlled only via DMA instructions (Instruction set summary). So to be able to issue DMA instructions - ie. writing them with their parameters to the DBGINST registers (up to 6 bytes) followed by writing zero to the DBGCMD Register - and to use other instructions than DMAGO, DMAKILL and DMASEV (when the DMAC is operating in the real-time), the DMA must be first set to the Non-secure state. I am still confused about all the information provided, so my questions are: Q1: What are the Secure and Non-secure states of the DMAC anyway? I can see there are 2 instances of the DMAC in the Register map: Non-Secure DMA Module (at 0xFFE00000) and Secure DMA Module (at 0xFFE01000). Does that mean, for example, I need to write to the Non-secure Debug registers when the DMAC started in Non-secure state, and write to the Secure Debug Registers when the DMAC is started in the Secure state? Q2: How do I change the state of the DMAC? I guess I have to put the DMAC to the reset state by writing the Reset Manager Module - PERMODRST register with the dma bit set to 1, write the System Manager Module - DMA - CTRL register wtih the mgrnonsecure bit set to 1 and then release the DMAC from reset using the PERMODRST register, is that right? Q3: Should the bits of the irqnonsecure field in the CTRL register be set or kept intact for the use with the f2h_dma_reqX signals from the FPGA? From both of the Intel and ARM Docs it seems that the interrupts are used for generating outputs from the DMAC (eg. when the transaction is finished to the peripheral), on the other hand the events get generated by the interrupt request signals or by the software (DMASEV) to be used internally, is that right? Q4: In the ARM Docs there is also mentioned the security state for the DMA manager thread, controlled by the boot_manager_ns signal. What is that signal and is it the same as the SYSMGR mgrnonsecure bit? Q5: So based on the table in the link you provided, I guess the f2h_dma_req0 to f2h_dma_req7 signals are mapped to the first 8 FPGA request interfaces. Are these interfaces enabbled by the first 8 bits in the event_irq_select field in the INTEN Interrupt Enable Register or is this register irrelevant for these signals? Also, based on my understanding, DMASEV (Send Event Instruction) is only used for software generated events to restart channels which issued DMAWFE (Wait For Event Instruction) - Do I understand it correctly that I need to issue DMAWFP (Wait For Peripheral Instruction) on the selected DMA channel to make it wait for the peripheral request f2h_dma_reqX (as suggested here)? Both the Intel and ARM Docs are REALLY confusing. Thank you for any help in advance.

Cyclone V - DMA Controller Intel FPGA IP Interrupts

15 Replies

vrbavojtech
New Contributor
3 years ago
Thanks for the information.

In the previous post I stated that I clear the PER2MODRST register bits (using mw.b command), but the DMA-330 is stuck in the Wait For Peripheral state (the waiting state) no matter if I set or reset the DMA request signal in the fabric.

Maybe the problem could be accessing DMA from the linux userspace?
Providing a minimal functioning example (eg. Quartus project) or at least the HPS configuration with the code would be really helpful

Thank you.
EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

Unfortunately we do not have the design example. You may explore and try the mentioned other DMA examples from below and the project in the first link:
https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/DE1-SoC
https://github.com/robertofem/CycloneVSoC-examples/tree/master/Baremetal-applications
https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-applications

I hope that I have provided the support and suffice information so that we are able to close the case.
EBERLAZARE_I_Intel
Regular Contributor
3 years ago
Hi,

I hope that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Cyclone V - DMA Controller Intel FPGA IP Interrupts

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