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vrbavojtech's avatar
vrbavojtech
Icon for New Contributor rankNew Contributor
3 years ago

Cyclone V - DMA Controller Intel FPGA IP Interrupts

Hello, I am currently trying to find out how to trigger a transfer of DMA Controller Intel FPGA IP (connected between f2h_sdram0 and on-chip 2-port RAM in QSYS) using an interrupt from the FPGA sid...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Unfortunately we do not have the design example. You may explore and try the mentioned other DMA examples from below and the project in the first link:

https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/DE1-SoC

https://github.com/robertofem/CycloneVSoC-examples/tree/master/Baremetal-applications

https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-applications


I hope that I have provided the support and suffice information so that we are able to close the case.