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vrbavojtech
New Contributor
New ContributorCyclone V - DMA Controller Intel FPGA IP Interrupts
Hello,
I am currently trying to find out how to trigger a transfer of DMA Controller Intel FPGA IP (connected between f2h_sdram0 and on-chip 2-port RAM in QSYS) using an interrupt from the FPGA sid...
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
I hope these info might help:
If you see below, there are 8 channels reset in the per2modrst register, and there should remain reset after POR:
https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410067767358.html
For e.g, let the HPS run and see the CSR0 state changes, make sure channel0/or any channel is waiting for peripheral0/any peripheral, DMA should be waiting.
The 8 channels reset in the per2modrst register, they remain reset after POR. Try to run something like:
"mm.b 0xffd05018"
After execution, the DMA330 should respond to the peripheral requests from FPGA.
Just for reference:
