Cyclone V - DMA Controller Intel FPGA IP Interrupts

Hi,

I hope these info might help:

If you see below, there are 8 channels reset in the per2modrst register, and there should remain reset after POR:

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410067767358.html

For e.g, let the HPS run and see the CSR0 state changes, make sure channel0/or any channel is waiting for peripheral0/any peripheral, DMA should be waiting.

The 8 channels reset in the per2modrst register, they remain reset after POR. Try to run something like:

"mm.b 0xffd05018"

After execution, the DMA330 should respond to the peripheral requests from FPGA.

Just for reference:

https://docs.rtems.org/doxygen/branches/master/group__ALT__DMA__PRG.html#ga4990f947286b37cfda315697743fdd57