Altera_Forum
Honored Contributor
11 years agoCyclone lll emulated LVDS IO
Hi,
Currently, we are using Cyclone lll FPGA for our application. We plan to interface LVDS output signals with sensor chip. We had assigned LVDS related O/P signal in bank 7 and bank 8(top banks). As per the Cyclone lll handbook, top(bank 7 & 8) and bottom(bank 3 & 4) only support for Emulated LVDS signals while others banks supports for both LVDS and as well as Emulated LVDS signals. For Emulated LVDS signal interface, is it compulsory to put external 3R resistor network? Presently we had not included any external 3R resistor network with emulated LVDS output signal but we had put only 100R resistor between differential signals. So, my concern is that whether FPGA provide proper signal interface with sensor chip or we need to redesign the board again. Will appreciate comments. Best Regards, Mayur Akbari