Forum Discussion
Altera_Forum
Honored Contributor
14 years agoIf the EPCS chip is close to the FPGA and you have short tracks between the two then there is no problem using 3.3V for the configuration pins, there is very little risk of overshoot.
IIRC the configuration pins don't have clamping diodes, and in that case there wouldn't be any problem driving them at 3.3V with a VCCIO of 2.5V. But if you can I think it's still a better habit to use the same VCCIO than the voltage you use on the I/O pins.