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Altera_Forum
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13 years ago

Cyclone IV vertical migration F484 1,0mm one size fits all

Edit: Issue has been solved, see my post with attachment down below.

Hi,

I was wondering, has anyone stumbled over a document describing a "one size fits all"-document for the vertical migration of Cyclone IV EP4CExx F484 1,0mm devices?

To clarify:

Intention: We want to migrate from Cyclone III to Cyclone IV

Problem: We want to be able to replace the FPGA (upsize) without changing the PCB design. Power supply will be made out to work even in "worst" case (EP4CE115), serial configuration EEPROM of course might need to change too, but that can be handled.

Now I know, that the bigger the FPGA gets, more and more I/Os are turned into supply pins (naturally: more logic, more power is needed). Also some differential pairs are moved around or disappear completely. And the list goes on.

What I want is, is a design that works for all EP4CExx F484 1,0mm devices in a vertical migration set. Meaning, it describes pins that are diff pairs in all devices, are I/Os in all devices, are clock pins in all devices, are supply in all devices, etc.

I am aware that this will probably greatly reduce the number of available I/Os, but that's OK, as I/Os aren't my greatest concern.

Vertical migration isn't as simple as it looked at first, but I want to make full use of it, since we need to redesign out PCB anyways.

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi KxAlpha..

    You are the second person in the last week, that has brought this up on the forum, and the should should Altera how much of an issue this really is, but they still don't get it.

    Altera's solution is to select all possible family members in the same package as "Migration Devices" with your IO's selected then compile the design.

    Quartus will then produce a .pin file or error out if you have an issue, that will describe all pins. and "should" handle all the migration issues.

    What I want is a pin-out excel sheet that does the same thing but they do these by device, and you end up running into the issues you described.

    My solution is to take all the device excel pin-outs for a particular package and do a merge for that package, so I know what the least common denominator is.

    I then use that spreadsheet to create an orcad symbol for the "migration" device.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    It shouldn't take but an hour or two to capture all the pin information in Excel to your liking and compile it together. I went through the exercise on the FG256 for the densities I was interested in for the CycIII and CycIV and noted the I/Os that were grounds in some packages, I/Os in others or similarly cross-functioned. You can glance at my Excel file at johnhandwork.com/Altera/EP3C4CEcommon.xlsx for ideas. I color coded based on VCC types and grounds where pns didn't match up and highlighted the pin names of those that didn't match between "adjacent" devices.

    The amount of cells can give you an idea why there may be no clean way to communicate the info but you can get from here to there without great trouble. It's just inconvenient.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    @johnhandwork

    Thanks, I got something quite similar to your approach from my Altera distributor over here, looks a little different and seems only to be working in between two devices. It looks almost as if made by Altera, that is why I was wondering in the first place. Sadly the guy I got it from is on vacation right now. I asked him the same thing as in the original post, if he comes up with something, I'll post it here.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    All righty,

    my distributors Altera FAE came thru and gave me a nice excel sheet he prepped for me. It basically shows you the I/O differences between all EP4CExxx in 484 pin packages. I added the common denominator column to it, so you know what you need to choose in order to be able to support all models of the package in question. Also I added a sheet for differential I/Os, there are a lot less possibilities. I had to rename most of them as pairs that are shared among different models rarely employ the same pin name combination.

    Hopefully that'll help some poor FPGA designers and especially PCB layouters.

    Please don't ask me for sheets for other families or packages, this one has taken me a few hours just for the diff-I/O sheet. But I guess you can use it as a template got others.