Cyclone IV unused input in 3.3V bank tied to +1.2V

Having the 3.3V inputs at 1.2V is probably no worse on an FPGA than with any other device. It is a voltage in the switching region, so chances are you will get random input toggles and higher current on those inputs.

If you already have a board with the 3.3V I/O tied to 1.2V, create an instance of SignalTap II and capture a long trace of the input values on those pins using say a 100MHz clock (use a PLL if needed).

Run a few tests where you have some noisy circuits nearby. My favorite is a power drill - press the button and place the chuck near your circuit board - if you've got a really crappy drill, you may even see arcing. Heat guns can also be pretty noisy / RFI generators. If the SignalTap II traces are all static high or low, even in the presence of nasty RFI, then you can indicate that the "error" is not terminal, but that the few tests you've performed are not exhaustive, so you would not recommend a production run of these boards.

I am sure you will do this ... as a "consultant" I would appraise the customer of how it should have been done (the VCCIO resistors trick, or your small power segment -> which probably turns out to be a whole layer due to the location of the pins). The customer can the decide whether to implement a board revision. Before they initiate the board revision, you should recommend they use these boards to check out the rest of the functions. For example, is the power system ok, does it support the transients it will expect? How good is the PLL decoupling? Is the JTAG wired correctly (to VCCA not VCCIO)? Given that one mistake was already made (albeit a tricky one to catch), they may as well check for other issues.

Cheers,

Dave